Module Signal.Unsigned

Unsigned vector operations (ie may operate on Bits.t or Signal.t directly).

val (+:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t

Addition. Arguments are extended appropriately and result is 1 bit wider to avoid truncation.

val (-:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t

Subtraction. Arguments are extended appropriately and result is 1 bit wider to avoid truncation.

val (*:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t

Multiplication.

Comparison operations

Arguments need not be the same width.

val (<:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val (>:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val (<=:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val (>=:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val (==:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val (<>:) : Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t -> Hardcaml__.Signal__type.t
val resize : Hardcaml__.Signal__type.t -> int -> Hardcaml__.Signal__type.t

Resize argument to given width. Appropriate extension is performed.

val truncate : Hardcaml__.Signal__type.t -> width:int -> (Hardcaml__.Signal__type.t, Hardcaml__.Signal__type.t) Hardcaml__.Comb_intf.with_valid2

Reduce the width of t to width bits. The result is valid if the value fits within width bits.