Reg_spec (hardcaml.hardcaml.Hardcaml.Signal.Reg

type t

val sexp_of_t : t -> Sexplib0.Sexp.t

val sexp_of_signal : Hardcaml__.Signal__type.t -> Sexplib0.Sexp.t

val create : 
  ?clock_edge:Edge.t ->
  ?reset:Hardcaml__.Signal__type.t ->
  ?reset_edge:Edge.t ->
  ?clear:Hardcaml__.Signal__type.t ->
  unit ->
  clock:Hardcaml__.Signal__type.t ->
  t

Create a Reg_spec.t. You must at a minimum provide a clock. clear and reset are optional. The clock_edge and reset_edge default to Rising.

val override : 
  ?clock:Hardcaml__.Signal__type.t ->
  ?clock_edge:Edge.t ->
  ?reset:Hardcaml__.Signal__type.t ->
  ?reset_edge:Edge.t ->
  ?clear:Hardcaml__.Signal__type.t ->
  t ->
  t

Override one or more fields of an existing Reg_spec.t.

val clock : t -> Hardcaml__.Signal__type.t

val clock_edge : t -> Edge.t

val reset : t -> Hardcaml__.Signal__type.t option

val reset_exn : t -> Hardcaml__.Signal__type.t

val reset_edge : t -> Edge.t

val clear : t -> Hardcaml__.Signal__type.t option

val clear_exn : t -> Hardcaml__.Signal__type.t