Hierarchy (hardcaml.hardcaml.Hardcaml.Hierarchy)

val fold : 
  Circuit.t ->
  Circuit_database.t ->
  init:'a ->
  f:
    ('a ->
      Circuit.t option ->
      Signal.t Signal.Type.Inst.Instantiation.t option ->
      'a) ->
  'a

Fold through every circuit and instantiation in a hierarchical design.

f will be passed the corresponding circuit if it exists in the database, and a Signal.instanation specification, unless the top most module.

val print : Circuit.t -> Circuit_database.t -> unit

module How_to_instantiate : sig ... end

module Caller_signal_type : sig ... end

module In_scope (I : Interface.S) (O : Interface.S) : sig ... end

Support for hierarchically structured Hardcaml designs. We extend the standard Interface.Create_fn pattern so that the create function also takes a Scope.t argument. This allows scoping of signal names and automatic recording of the design in a Circuit_database.t.

module In_clocked_scope
  (I : Interface.S_with_clock_domains)
  (O : Interface.S_with_clock_domains) : 
  sig ... end