Rtl (hardcaml.hardcaml.Hardcaml.Rtl)

include module type of struct include Rtl end

module Language : sig ... end

module Circuit_instance : sig ... end

module Hierarchical_circuits : sig ... end

Generated top levels and sub circuits.

val create : 
  ?database:Circuit_database.t ->
  ?config:Hardcaml__.Rtl_config.t ->
  Language.t ->
  Circuit.t list ->
  Hierarchical_circuits.t list

Create a hierarchical set of circuit instances that can be traversed to get the RTL implementation(s).

val full_hierarchy : Hierarchical_circuits.t list -> Rope.t

Create RTL for the top level circuits and everything it instantiates.

val top_levels_only : Hierarchical_circuits.t list -> Rope.t

Create RTL just for the top level circuits.

val top_levels_as_blackboxes : Hierarchical_circuits.t list -> Rope.t

Create blackboxes of the top level circuits.

val top_levels_and_blackboxes : Hierarchical_circuits.t list -> Rope.t

Create RTL for the top level circuits, and black boxes for the things they instantiate.

val print : 
  ?database:Circuit_database.t ->
  ?config:Hardcaml__.Rtl_config.t ->
  Language.t ->
  Circuit.t ->
  unit

print RTL for a circuit, with optional hierarchy (if database is provided), to stdout.

module Digest : sig ... end

module Ast : sig ... end

module Name : sig ... end

module Verilog : sig ... end

module Vhdl : sig ... end

module Config : sig ... end