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Module `Hardcaml.Assertions`

Assertions within Hardcaml simulations.

There are a few steps needed to enable assertions:

1. pass trace_properties:true to Scope.create 2. enable them in the Circuit.Config (see circuit_config_with_assertions) 3. (optionally) attach assertion tracing to the simulation (see trace)

type t

val sexp_of_t : t -> Sexplib0.Sexp.t

module Violated_or_not : sig ... end

val circuit_config_with_assertions : 
  ?config:Circuit.Config.t ->
  Scope.t ->
  Circuit.Config.t

Return a circuit config with assertions enabled.

val trace : 
  ('i, 'o) Cyclesim.t ->
  Hardcaml__.Assertion_manager.t option ->
  t * ('i, 'o) Cyclesim.t

Connect to a simulator and record all assertions.

val results : t -> Violated_or_not.t Base.Map.M(Core.String).t option

Return assertions fired during a simulation. Printing t as a sexp displays these results.

val add : Scope.t -> string -> Signal.t -> unit

Add an assertion to the scope's assertion manager.

module Always : sig ... end