Module Hardcaml.Cyclesim

Cycle accurate simulator

module Port_list : sig ... end
module Traced : sig ... end
module Node : sig ... end
module Reg : sig ... end
module Memory : sig ... end

Read and write access for memories. They have much the same API as Nodes. and Regs except for an extra address argument.

module Config : sig ... end
type ('i, 'o) t

Base type of the cycle based simulators

type t_port_list = (Port_list.t, Port_list.t) t
val circuit : (_, _) t -> Circuit.t option

Returns the circuit used to compile the simulation.

val cycle : ?n:int -> (_, _) t -> unit

Advance by n clock cycles (check->comb->seq->comb). n defaults to 1.

val cycle_check : (_, _) t -> unit

Check inputs are valid before a simulation cycle

val cycle_before_clock_edge : (_, _) t -> unit

Update combinatorial logic before clock edge and relative to new inputs.

val cycle_at_clock_edge : (_, _) t -> unit

Update sequential logic - registers and memories.

val cycle_after_clock_edge : (_, _) t -> unit

Update combinatorial logic after clock edge

val clock_mode : (_, _) t -> [ `All_one_domain | `By_input_clocks ]

Clock mode specified in the config. See the Cyclesim0.Config of an explanation of each mode

val cycle_until_clocks_aligned : (_, _) t -> unit

Repeatedly call cycle until all clocks specified in the config are aligned with their periods.

val reset : (_, _) t -> unit

Reset simulator

val raise_after_timeout : ?message:string -> here:lexing_position -> ('i, 'o) t -> timeout:int -> ('i, 'o) t

Attach to a simulator and cause it to raise after the given number of steps. Resetting the simulation will also reset the timeouts.

val with_timeout : ?message:string -> here:lexing_position -> timeout:int -> f:(('i, 'o) t -> 'c) -> ('i, 'o) t -> 'c

Raise if the provided callback f takes more than timeout cycles to execute.

val in_port : (_, _) t -> string -> Bits.t ref

Get input port given a name

val traced : (_, _) t -> Traced.t

Signals and their unique (mangled) names to be traced by the simulation. Includes both IO ports and internal signals - the latter are accessible via the lookup function.

val out_port : ?clock_edge:Side.t -> (_, _) t -> string -> Bits.t ref

Get output port given a name. If clock_edge is Before the outputs are computed prior to the clock edge - After means the outputs are computed after the clock edge.

val inputs : ('i, _) t -> 'i
val outputs : ?clock_edge:Side.t -> (_, 'o) t -> 'o
val in_ports : (_, _) t -> Port_list.t
val out_ports : ?clock_edge:Side.t -> (_, _) t -> Port_list.t
val lookup_node : (_, _) t -> Traced.internal_signal -> Node.t option

Current value of an internal (combinational) node within the simulator.

val lookup_node_by_name : (_, _) t -> string -> Node.t option
val lookup_node_or_reg : (_, _) t -> Traced.internal_signal -> Node.t option
val lookup_node_or_reg_by_name : (_, _) t -> string -> Node.t option
val lookup_reg : (_, _) t -> Traced.internal_signal -> Reg.t option

Peek at internal registers, return Some _ if it's present. Note that the node must marked as traced in Cyclesim.Config.t when creating simulations for this to return (Some _). Writing to the Bits.Mutable.t will change the simulation internal node's value and affect the results of simulation.

val lookup_reg_by_name : (_, _) t -> string -> Reg.t option
val lookup_mem : (_, _) t -> Traced.internal_signal -> Memory.t option

Similar to lookup_data, but for memories. This is very useful for initializing memory contents without having to simulate the entire circuit.

val lookup_mem_by_name : (_, _) t -> string -> Memory.t option
val create : ?config:Config.t -> Circuit.t -> t_port_list

construct a simulator from a circuit

module Combine_error : sig ... end
val combine : ?port_sets_may_differ:bool -> ?on_error:(Combine_error.t -> unit) -> ('i, 'o) t -> ('i, 'o) t -> ('i, 'o) t

Combine 2 simulators. The inputs are set on the 1st simulator and copied to the 2nd. Outputs are checked and on_error is called if a difference is found. By default, on_error raises.

The simulators should have the same input and output port sets, unless port_sets_may_differ is true, in which case only ports which exist on both simulators are checked.

module With_interface (I : Interface.S) (O : Interface.S) : sig ... end
module Private : sig ... end