Module Cyclesim.Traced

type io_port = {
  1. signal : Signal.t;
  2. name : string;
}
val sexp_of_io_port : io_port -> Sexplib0.Sexp.t
type internal_signal = {
  1. signal : Signal.t;
  2. mangled_names : string list;
}
val sexp_of_internal_signal : internal_signal -> Sexplib0.Sexp.t
type t = {
  1. input_ports : io_port list;
  2. output_ports : io_port list;
  3. internal_signals : internal_signal list;
}
val sexp_of_t : t -> Sexplib0.Sexp.t
val to_io_port : Signal.t -> io_port