Of_bits (hardcaml.hardcaml.Hardcaml.Enum.Make_binary.Of

type comb = Bits.t

type t = comb t

val sexp_of_t : comb t -> Sexplib0.Sexp.t

val assert_widths : comb t -> unit

Raise if the widths of t do not match those specified in the interface.

val validate : comb t -> unit

Checks the port widths of the signals in the interface. Raises if they mismatch.

val of_int_trunc : int -> comb t

Each field is set to the constant integer value provided.

val of_unsigned_int : int -> comb t

val of_signed_int : int -> comb t

val zero : unit -> comb t

Identical to of_unsigned_int 0

val pack : ?rev:bool -> comb t -> comb

Pack interface into a vector.

val unpack : ?rev:bool -> comb -> comb t

Unpack interface from a vector.

val mux : comb -> comb t list -> comb t

Multiplex a list of interfaces.

val mux2 : comb -> comb t -> comb t -> comb t

val concat : comb t list -> comb t

Concatenate a list of interfaces.

val priority_select : 
  ((comb, comb t) Comb.with_valid2 list ->
    (comb, comb t) Comb.with_valid2)
    Comb.optional_branching_factor

val priority_select_with_default : 
  ((comb, comb t) Comb.with_valid2 list ->
    default:comb t ->
    comb t)
    Comb.optional_branching_factor

val onehot_select : 
  ((comb, comb t) Comb.with_valid2 list ->
    comb t)
    Comb.optional_branching_factor

val widths : t -> int t

Actual bit widths of each field.

val of_ints_trunc : int t -> t

of_ints_trunc c sets each field to the integer value in c using the declared field bit width.

val of_unsigned_ints : int t -> t

val of_signed_ints : int t -> t

val is : t -> Cases.t -> Bits.t

val (==:) : t -> t -> Bits.t

val of_enum : Cases.t -> Bits.t outer

val of_raw : Bits.t -> Bits.t outer

val match_ : 
  ?default:Bits.t ->
  Bits.t outer ->
  (Cases.t * Bits.t) list ->
  Bits.t