Module Functional.Make

Parameters

Signature

module Before_and_after_edge = Hardcaml.Before_and_after_edge
module I = I
module O = O
module O_data : sig ... end

A testbench takes the circuit's output as its input and produces its output as input for the circuit. An 'a t describes a testbench computation that takes zero or more steps and produces a value of type 'a.

include Core.Monad.S with type 'a t := 'a t
val return : 'a 'i 'p 'q. 'a -> 'a t

Convert a value to a t.

val map : 'a 'b 'i 'j 'p 'q. 'a t -> f:('a -> 'b) -> 'b t

Transforms the contents of a t.

val bind : 'a 'b 'i 'j 'k 'p 'q. 'a t -> f:('a -> 'b t) -> 'b t

Sequences computations. bind t ~f computes f v for value(s) v in t. Well-behaved monads satisfy these "laws" (where ( >>= ) is the infix bind operator):

  • map t ~f is equivalent to bind t ~f:(fun x -> return (f x))
  • return x >>= f is equivalent to f x
  • t >>= return is equivalent to t
  • (t >>= f) >>= g is equivalent to t >>= fun x -> f x >>= g
val join : 'a 'i 'j 'k 'p 'q. 'a t t -> 'a t

Combines nested t into just one layer. Equivalent to bind t ~f:Fn.id.

val ignore_m : 'a 'i 'j 'p 'q. 'a t -> unit t

Ignores contained values of t. Equivalent to map t ~f:ignore.

val all : 'a 'i 'p 'q. 'a t list -> 'a list t

Combines a list of t.

val all_unit : 'i 'p 'q. unit t list -> unit t

Combines a list of t whose contents are unimportant.

val (>>=) : 'a 'b 'i 'j 'k 'p 'q. 'a t -> ('a -> 'b t) -> 'b t

Infix bind.

val (>>|) : 'a 'b 'i 'j 'p 'q. 'a t -> ('a -> 'b) -> 'b t

Infix map.

module Monad_infix : sig ... end
module Let_syntax : sig ... end
val cycle : ?num_cycles:int -> I_data.t -> O_data.t t

cycle i_data ~num_cycles waits for num_cycles cycles of the simulator to run, applying i_data to the simulator input ports, and returns the output computed in the final cycle. cycle raises if num_cycles < 1.

val for_ : int -> int -> (int -> unit t) -> unit t

for_ i j f does f i, f (i+1), ... f j in sequence. If j < i, then for_ i j immediately returns unit.

val delay : ?num_cycles:int -> I_data.t -> unit t

delay inputs ~num_cycles applies inputs for num_cycles clock cycles and then returns unit. delay raises if num_cycles < 0.

val spawn : ?update_children_after_finish:bool -> ?period:int -> (O_data.t -> 'a t) -> ('a, I_data.t) finished_event t

Launch a new task within the current simulation step.

val merge_inputs : parent:I_data.t -> child:I_data.t -> I_data.t

merge_inputs ~parent ~child merges the child inputs into the parent. If a child input is empty, the parent's value is used.

val spawn_io : ?update_children_after_finish:bool -> ?period:int -> inputs:(parent:'i -> child:I_data.t -> 'i) -> outputs:('o -> Hardcaml.Bits.t O.t) -> (O_data.t -> 'a t) -> (('a, I_data.t) finished_event, 'o Before_and_after_edge.t, 'i) Hardcaml_step_testbench_kernel.Step_monad.t

Launch a task from a testbench with a cycle function taking 'i to 'o. The inputs and outputs arguments should construct I_data.t and O_data.t from the types of the child testbench.

See documentation of spawn for an explaination of update_children_after_finish.

val create_io_ports_for_imperative : ('i, 'o) Hardcaml.Cyclesim.t -> inputs:('i -> Hardcaml.Bits.t Core.ref I.t) -> outputs:('o -> Hardcaml.Bits.t Core.ref O.t) -> (Hardcaml.Bits.t Core.ref I.t, Hardcaml.Bits.t Core.ref O.t) Io_ports_for_imperative.t

Create io ports to be used with spawn_from_imperative from a simulator.

val spawn_from_imperative : ?update_children_after_finish:bool -> ?period:int -> (Hardcaml.Bits.t Core.ref I.t, Hardcaml.Bits.t Core.ref O.t) Io_ports_for_imperative.t -> (O_data.t -> 'a t) -> (('a, I_data.t) finished_event, unit Before_and_after_edge.t, unit) Hardcaml_step_testbench_kernel.Step_monad.t

Similar to spawn_io, but for a task (which uses the functional step testbench) from a task that's using the imperative step testbench.

val exec_never_returns_from_imperative : ?update_children_after_finish:bool -> ?period:int -> (Hardcaml.Bits.t Core.ref I.t, Hardcaml.Bits.t Core.ref O.t) Io_ports_for_imperative.t -> (O_data.t -> Core.never_returns t) -> (Core.never_returns, unit Before_and_after_edge.t, unit) Hardcaml_step_testbench_kernel.Step_monad.t

Spawns a functional step testbench infinite loop from a imperative testbench, and block forever.

This semantically similar to spawn_from_imperative >>= wait_for under the hood but with nicer types.

val wait_for : ('a, 'b) finished_event -> 'a t

Wait for the given event to occur, and extract its return value.

val wait_for_with_timeout : ('a, 'b) finished_event -> timeout_in_cycles:int -> 'a option t

Like wait_for except it stops waiting after timeout_in_cycles and returns None. Note that the spawned task continues to execute.

val input_hold : Hardcaml.Bits.t I.t

Call run ~input_default:input_hold to hold inputs their previous value if they are unset by tasks in the testbench.

val input_zero : Hardcaml.Bits.t I.t

Call run ~input_default:input_zero to set inputs to zero if unset by tasks in the testbench.

val forever : (unit -> unit t) -> Core.never_returns t

Call forever f to run f forever. forever never returns.

To prevent starving other tasks, it's the caller's responsibility to ensure that f calls cycle or delay under the hood!

val forever_unit : (unit -> unit t) -> unit t

Similar to forever, but returns unit, for convenience.

val never : Core.never_returns t
val run_effectful_computation : ((O_data.t, I_data.t) Digital_components.Step_effect.Handler.t @ local -> 'a) -> 'a t
module List : sig ... end
module Array : sig ... end