Derive_interface_from_map2 (ppx_hardcaml.ppx_hardcaml.runtime.Ppx_hardcaml_runtime.Derive_interface_from

Parameters

module X : sig ... end

Signature

val compare : ('a -> 'a -> int) -> 'a X.t -> 'a X.t -> int

val compare__local : 
  ('a @ local -> ('a @ local -> int) @ local) ->
  'a X.t @ local ->
  ('a X.t @ local ->
  int) @ local

val sexp_of_t : ('a -> Sexplib0.Sexp.t) -> 'a X.t -> Sexplib0.Sexp.t

val iter : 'a X.t -> f:('a -> unit) @ local -> unit

val iter2 : 'a X.t -> 'b X.t -> f:('a -> ('b -> unit) @ local) @ local -> unit

val map : 'a X.t -> f:('a -> 'b) @ local -> 'b X.t

val map2 : 'a X.t -> 'b X.t -> f:('a -> ('b -> 'c) @ local) @ local -> 'c X.t

val to_list : 'a X.t -> 'a list

val port_names_and_widths : (string * int) X.t

val equal : ('a -> 'a -> bool) -> 'a X.t -> 'a X.t -> bool

val equal__local : 
  ('a @ local -> ('a @ local -> bool) @ local) ->
  'a X.t @ local ->
  ('a X.t @ local ->
  bool) @ local

val port_names : string X.t

val port_widths : int X.t

val const : 'a -> 'a X.t

type tag

val equal_tag : tag -> tag -> bool

val equal_tag__local : tag @ local -> (tag @ local -> bool) @ local

val tags : tag X.t

val to_alist : 'a X.t -> (tag * 'a) list

val of_alist : (tag * 'a) list -> 'a X.t

val sum_of_port_widths : int

module Unsafe_assoc_by_port_name : sig ... end

val zip : 'a X.t -> 'b X.t -> ('a * 'b) X.t

val zip3 : 'a X.t -> 'b X.t -> 'c X.t -> ('a * 'b * 'c) X.t

val zip4 : 'a X.t -> 'b X.t -> 'c X.t -> 'd X.t -> ('a * 'b * 'c * 'd) X.t

val zip5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  ('a * 'b * 'c * 'd * 'e) X.t

val map3 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  f:('a -> ('b -> ('c -> 'd) @ local) @ local) @ local ->
  'd X.t

val map4 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  f:('a -> ('b -> ('c -> ('d -> 'e) @ local) @ local) @ local) @ local ->
  'e X.t

val map5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  f:
    ('a -> ('b -> ('c -> ('d -> ('e -> 'f) @ local) @ local) @ local) @ local) @ local ->
  'f X.t

val iter3 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  f:('a -> ('b -> ('c -> unit) @ local) @ local) @ local ->
  unit

val iter4 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  f:('a -> ('b -> ('c -> ('d -> unit) @ local) @ local) @ local) @ local ->
  unit

val iter5 : 
  'a X.t ->
  'b X.t ->
  'c X.t ->
  'd X.t ->
  'e X.t ->
  f:
    ('a ->
      ('b ->
      ('c ->
      ('d ->
      ('e ->
      unit) @ local) @ local) @ local) @ local) @ local ->
  unit

val fold : 
  'a X.t ->
  init:'acc ->
  f:('acc -> ('a -> 'acc) @ local) @ local ->
  'acc

val fold2 : 
  'a X.t ->
  'b X.t ->
  init:'acc ->
  f:('acc -> ('a -> ('b -> 'acc) @ local) @ local) @ local ->
  'acc

val scan : 
  'a X.t ->
  init:'acc ->
  f:('acc -> ('a -> 'acc * 'b) @ local) @ local ->
  'b X.t

val scan2 : 
  'a X.t ->
  'b X.t ->
  init:'acc ->
  f:('acc -> ('a -> ('b -> 'acc * 'c) @ local) @ local) @ local ->
  'c X.t

val offsets : ?rev:bool -> unit -> int X.t

val of_interface_list : 'a X.t list -> 'a list X.t

val to_interface_list : 'a list X.t -> 'a X.t list

module All (M : Base.Monad.S) : sig ... end

val or_error_all : 'a Core.Or_error.t X.t -> 'a X.t Core.Or_error.t

module type Comb = sig ... end

module Make_comb (Comb : Hardcaml.Comb.S) : sig ... end

module Of_bits : sig ... end

module Of_signal : sig ... end

module Of_clocked_signal : sig ... end

module Of_always : sig ... end

module Names_and_widths : sig ... end

val wave_formats : Hardcaml.Wave_format.t X.t