Module Hardcaml_waveterm_kernel.Port

Simulation port description.

module Type : sig ... end
type t = {
  1. type_ : Type.t;
  2. port_name : Port_name.t;
  3. width : Base.int;
}
include Ppx_compare_lib.Comparable.S with type t := t
val compare : t -> t -> int
include Ppx_compare_lib.Comparable.S__local with type t := t
val sexp_of_t : t -> Sexplib0.Sexp.t
include Ppx_compare_lib.Equal.S with type t := t
val equal : t -> t -> bool
include Ppx_compare_lib.Equal.S__local with type t := t