Module Key_actions.Of_signal

type 'a interface := 'a t
include Comb with type comb = Hardcaml.Signal.t
type comb = Hardcaml.Signal.t
type t = comb t
val sexp_of_t : comb t -> Sexplib0.Sexp.t
val assert_widths : comb t -> unit

Raise if the widths of t do not match those specified in the interface.

val validate : comb t -> unit

Checks the port widths of the signals in the interface. Raises if they mismatch.

val of_int_trunc : int -> comb t

Each field is set to the constant integer value provided.

val of_unsigned_int : int -> comb t
val of_signed_int : int -> comb t
val zero : unit -> comb t

Identical to of_unsigned_int 0

val pack : ?rev:bool -> comb t -> comb

Pack interface into a vector.

val unpack : ?rev:bool -> comb -> comb t

Unpack interface from a vector.

val mux : comb -> comb t list -> comb t

Multiplex a list of interfaces.

val mux2 : comb -> comb t -> comb t -> comb t
val concat : comb t list -> comb t

Concatenate a list of interfaces.

val priority_select_with_default : ((comb, comb t) Hardcaml.Comb.with_valid2 list -> default:comb t -> comb t) Hardcaml.Comb.optional_branching_factor
val widths : t -> int t

Actual bit widths of each field.

val of_ints_trunc : int t -> t

of_ints_trunc c sets each field to the integer value in c using the declared field bit width.

val of_unsigned_ints : int t -> t
val of_signed_ints : int t -> t
val wires : ?named:bool -> ?from:t -> unit -> t

Create a wire for each field. If named is true then wires are given the RTL field name. If from is provided the wire is attached to each given field in from.

Defines a register over values in this interface. enable defaults to vdd.

val reg : ?enable:Hardcaml__.Signal__type.t -> ?initialize_to:bits_t -> ?reset_to:bits_t -> ?clear:Hardcaml__.Signal__type.t -> ?clear_to:t -> Hardcaml__.Signal.Reg_spec.t -> t -> t
val cut_through_reg : ?initialize_to:bits_t -> ?reset_to:bits_t -> ?clear:Hardcaml__.Signal__type.t -> ?clear_to:t -> Hardcaml__.Signal.Reg_spec.t -> enable:Hardcaml__.Signal__type.t -> t -> t

Defines a cut through register over values in this interface.

val pipeline : ?attributes:Hardcaml.Rtl_attribute.t list -> ?enable:Hardcaml__.Signal__type.t -> ?initialize_to:bits_t -> ?reset_to:bits_t -> ?clear:Hardcaml__.Signal__type.t -> ?clear_to:t -> Hardcaml__.Signal.Reg_spec.t -> n:int -> t -> t

Defines a register pipeline over values in this interface. enable defaults to vdd and attributes defaults to an empty list.

val assign : t -> t -> unit
val (<--) : t -> t -> unit
val inputs : unit -> t

inputs t is wires () ~named:true.

val outputs : t -> t

outputs t is wires () ~from:t ~named:true.

val apply_names : ?prefix:string -> ?suffix:string -> ?naming_op: (loc:lexing_position -> Hardcaml__.Signal__type.t -> string -> Hardcaml__.Signal__type.t) -> t -> t

Apply name to field of the interface. Add prefix and suffix if specified.

val __ppx_auto_name : t -> string -> t